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IDT5T905 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFERTM
FEATURES:
* * * * * * * * *
IDT5T905
DESCRIPTION:
Guaranteed Low Skew < 25ps (max) Very low duty cycle distortion High speed propagation delay < 2.5ns. (max) Up to 250MHz operation Very low CMOS power levels 1.5V VDDQ for HSTL interface Hot insertable and over-voltage tolerant inputs 3-level inputs for selectable interface Selectable HSTL, eHSTL, 1.8V / 2.5V LVTTL, or LVEPECL input interface * Selectable differential or single-ended inputs and five singleended outputs * 2.5V VDD * Available in TSSOP package
The IDT5T905 2.5V single data rate (SDR) clock buffer is a user-selectable single-ended or differential input to five single-ended outputs buffer built on advanced metal CMOS technology. The SDR clock buffer fanout from a single or differential input to five single-ended outputs reduces the loading on the preceding driver and provides an efficient clock distribution network. The IDT5T905 can act as a translator from a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended 1.8V/2.5V LVTTL input to HSTL, eHSTL, 1.8V/2.5V LVTTL outputs. Selectable interface is controlled by 3-level input signals that may be hard-wired to appropriate high-mid-low levels. Multiple power and grounds reduce noise.
* Clock and signal distribution
APPLICATIONS:
FUNCTIONAL BLOCK DIAGRAM
TxS GL G
OUTPUT CONTROL
Q1
RxS A A/VREF
OUTPUT CONTROL
Q2
OUTPUT CONTROL
Q3
OUTPUT CONTROL
Q4
OUTPUT CONTROL
Q5
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
FEBRUARY 2003
DSC-5942/25
(c) 2003 Integrated Device Technology, Inc.
IDT5T905 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDD Description Power Supply Voltage(2) Output Power Input Voltage Output Voltage(3) Reference Voltage(3) Storage Temperature Junction Temperature Supply(2) Max -0.5 to +3.6 -0.5 to +3.6 -0.5 to +3.6 -0.5 to VDDQ +0.5 -0.5 to +3.6 -65 to +165 150 Unit V V V V V C C VDDQ VI VO VREF TSTG TJ
GL VDD GND G VDDQ Q1 A/VREF A Q5 VDDQ GND VDD VDD RxS
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
GND VDDQ GND GND VDDQ Q2 GND Q3 Q4 VDDQ GND GND VDDQ TxS
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDDQ and VDD internally operate independently. No power sequencing requirements need to be met. 3. Not to exceed 3.6V.
CAPACITANCE(1,2) (TA = +25C, F = 1.0MHz)
Symbol CIN Parameter Input Capacitance Min Typ. 3.5 Max. Unit pF
--
--
TSSOP TOP VIEW
NOTES: 1. This parameter is measured at characterization but not tested. 2. Capacitance applies to all inputs except RxS and TxS.
RECOMMENDED OPERATING RANGE
Symbol TA VDD(1) VDDQ(1) VT Description Ambient Operating Temperature Internal Power Supply Voltage HSTL Output Power Supply Voltage Extended HSTL and 1.8V LVTTL Output Power Supply Voltage 2.5V LVTTL Output Power Supply Voltage Termination Voltage Min. -40 2.4 1.4 1.65 Typ. +25 2.5 1.5 1.8 VDD VDDQ / 2 Max. +85 2.6 1.6 1.95 Unit C V V V V V
NOTE: 1. All power supplies should operate in tandem. If VDD or VDDQ is at maximum, then VDDQ or VDD (respectively) should be at maximum, and vice-versa.
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IDT5T905 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol A A/VREF I/O I I Type Adjustable(1) Adjustable(1) Description Clock input. A is the "true" side of the differential clock input. If operating in single-ended mode, A is the clock input. Complementary clock input. A/VREF is the "complementary" side of A if the input is in differential mode. If operating in single-ended mode, A/VREF is connected to GND. For single-ended operation in differential mode, A/VREF should be set to the desired toggle voltage for A: 2.5V LVTTL VREF = 1250mV 1.8V LVTTL, eHSTL VREF = 900mV HSTL VREF = 750mV LVEPECL VREF = 1082mV Gate control for Qn outputs. When G is LOW, these outputs are enabled. When G is HIGH, these outputs are asynchronously disabled to the level designated by GL(4). Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs disable LOW. Clock outputs Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) clock input or differential (LOW) clock input Sets the drive strength of the output drivers to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) or HSTL (LOW) compatible. Used in conjunction with VDDQ to set the interface levels. Power supply for the device core and inputs Power supply for the device outputs. When utilizing 2.5V LVTTL outputs, VDDQ should be connected to VDD. Power supply return for all power
G GL Qn RxS TxS VDD VDDQ GND
I I O I I
LVTTL(5) LVTTL(5) Adjustable(2) 3 Level(3) 3 Level(3) PWR PWR PWR
NOTES: 1. Inputs are capable of translating the following interface standards. User can select between: Single-ended 2.5V LVTTL levels Single-ended 1.8V LVTTL levels or Differential 2.5V/1.8V LVTTL levels Differential HSTL and eHSTL levels Differential LVEPECL levels 2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage. 3. 3 level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over-voltage tolerant. 4. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the possibility of runt pulses or be able to tolerate them in down stream circuitry. 5. Pins listed as LVTTL inputs will accept 2.5V signals when RxS = HIGH or 1.8V signals when RxS = LOW or MID.
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IDT5T905 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
INPUT/OUTPUT SELECTION(1)
Input 2.5V LVTTL SE 1.8V LVTTL SE 2.5V LVTTL DSE 1.8V LVTTL DSE LVEPECL DSE eHSTL DSE HSTL DSE 2.5V LVTTL DIF 1.8V LVTTL DIF LVEPECL DIF eHSTL DIF HSTL DIF 2.5V LVTTL SE 1.8V LVTTL SE 2.5V LVTTL DSE 1.8V LVTTL DSE LVEPECL DSE eHSTL DSE HSTL DSE 2.5V LVTTL DIF 1.8V LVTTL DIF LVEPECL DIF eHSTL DIF HSTL DIF 1.8V LVTTL Output 2.5V LVTTL Input 2.5V LVTTL SE 1.8V LVTTL SE 2.5V LVTTL DSE 1.8V LVTTL DSE LVEPECL DSE eHSTL DSE HSTL DSE 2.5V LVTTL DIF 1.8V LVTTL DIF LVEPECL DIF eHSTL DIF HSTL DIF 2.5V LVTTL SE 1.8V LVTTL SE 2.5V LVTTL DSE 1.8V LVTTL DSE LVEPECL DSE eHSTL DSE HSTL DSE 2.5V LVTTL DIF 1.8V LVTTL DIF LVEPECL DIF eHSTL DIF HSTL DIF HSTL Output eHSTL
NOTE: 1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations of input and output interfaces. Single-Ended (SE) inputs in a single-ended mode require the A/VREF pin to be connected to GND. Differential Single-Ended (DSE) is for single-ended operation in differential mode, requiring a VREF. Differential (DIF) inputs are used only in differential mode.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol VIHH VIMM VILL I3 Parameter Input HIGH Voltage Level(1) Input MID Voltage Level(1) Input LOW Voltage Level(1) 3-Level Input DC Current (RxS, TxS) Test Conditions 3-Level Inputs Only 3-Level Inputs Only 3-Level Inputs Only VIN = VDD VIN = VDD/2 VIN = GND Min. VDD - 0.4 VDD/2 - 0.2 -- -- -50 -200 Max -- VDD/2 + 0.2 0.4 200 +50 -- Unit V V V A
HIGH Level MID Level LOW Level
NOTE: 1. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias unconnected unputs to VDD/2.
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IDT5T905 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR HSTL(1)
Symbol Parameter Input Characteristics IIH Input HIGH Current(9) IIL Input LOW Current(9) VIK Clamp Diode Voltage VIN DC Input Voltage VDIF DC Differential Voltage(2,8) VCM DC Common Mode Input Voltage(3,8) VIH DC Input HIGH(4,5,8) VIL DC Input LOW(4,6,8) Single-Ended Reference Voltage(4,8) VREF Output Characteristics VOH Output HIGH Voltage VOL Output LOW Voltage Test Conditions VDD = 2.6V VI = VDDQ/GND VDD = 2.6V VI = GND/VDDQ VDD = 2.4V, IIN = -18mA Min. -- -- -- - 0.3 0.2 680 VREF + 100 -- -- VDDQ - 0.4 VDDQ - 0.1 -- -- Typ.(7) -- -- - 0.7 Max 5 5 - 1.2 +3.6 -- 900 -- VREF - 100 -- -- -- 0.4 0.1 Unit A V V V mV mV mV mV V V V V
750
750
IOH = -8mA IOH = -100A IOL = 8mA IOL = 100A
NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 4. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF. 5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 6. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 7. Typical values are at VDD = 2.5V, VDDQ = 1.5V, +25C ambient. 8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
POWER SUPPLY CHARACTERISTICS FOR HSTL OUTPUTS(1)
Symbol IDDQ IDDQQ IDDD IDDDQ ITOT ITOTQ Parameter Quiescent VDD Power Supply Current Quiescent VDDQ Power Supply Current Dynamic VDD Power Supply Current per Output Dynamic VDDQ Power Supply Current per Output Total Power VDD Supply Current Total Power VDDQ Supply Current Test Conditions(2) VDDQ = Max., Reference Clock = LOW(3) Outputs enabled, All outputs unloaded VDDQ = Max., Reference Clock = LOW(3) Outputs enabled, All outputs unloaded VDD = Max., VDDQ = Max., CL = 0pF VDD = Max., VDDQ = Max., CL = 0pF VDDQ = 1.5V, FREFERENCE CLOCK = 100MHz, CL = 15pF VDDQ = 1.5V, FREFERENCE CLOCK = 250MHz, CL = 15pF VDDQ = 1.5V, FREFERENCE CLOCK = 100MHz, CL = 15pF VDDQ = 1.5V, FREFERENCE CLOCK = 250MHz, CL = 15pF Typ. 20 0.1 10 15 20 25 15 30 Max 30 0.3 20 30 30 40 30 60 Unit mA mA A/MHz A/MHz mA mA
NOTES: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. The termination resistors are excluded from these measurements. 3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
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IDT5T905 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL
Symbol VDIF VX VTHI tR, tF Parameter Input Signal Swing(1) Differential Input Signal Crossing Point Input Signal Edge Rate
(4) (2)
Value 1 750 Crossing Point 1
Units V mV V V/ns
Input Timing Measurement Reference Level(3)
NOTES: 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions. 2. A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR eHSTL(1)
Symbol Parameter Input Characteristics IIH Input HIGH Current(9) IIL Input LOW Current(9) VIK Clamp Diode Voltage VIN DC Input Voltage VDIF DC Differential Voltage(2,8) VCM DC Common Mode Input Voltage(3,8) VIH DC Input HIGH(4,5,8) VIL DC Input LOW(4,6,8) VREF Single-Ended Reference Voltage(4,8) Output Characteristics VOH Output HIGH Voltage VOL Output LOW Voltage Test Conditions VDD = 2.6V VI = VDDQ/GND VDD = 2.6V VI = GND/VDDQ VDD = 2.4V, IIN = -18mA Min. -- -- -- - 0.3 0.2 800 VREF + 100 -- -- VDDQ - 0.4 VDDQ - 0.1 -- -- Typ.(7) -- -- - 0.7 Max 5 5 - 1.2 +3.6 -- 1000 -- VREF - 100 -- -- -- 0.4 0.1 Unit A V V V mV mV mV mV V V V V
900
900
IOH = -8mA IOH = -100A IOL = 8mA IOL = 100A
NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 4. For single-ended operation, in a differential mode, A/VREF is tied to the DC voltage VREF. 5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 6. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 7. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25C ambient. 8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 9. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
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IDT5T905 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS FOR eHSTL OUTPUTS(1)
Symbol IDDQ IDDQQ IDDD IDDDQ ITOT ITOTQ Parameter Quiescent VDD Power Supply Current Quiescent VDDQ Power Supply Current Dynamic VDD Power Supply Current per Output Dynamic VDDQ Power Supply Current per Output Total Power VDD Supply Current Total Power VDDQ Supply Current Test Conditions(2) VDDQ = Max., Reference Clock = LOW(3) Outputs enabled, All outputs unloaded VDDQ = Max., Reference Clock = LOW(3) Outputs enabled, All outputs unloaded VDD = Max., VDDQ = Max., CL = 0pF VDD = Max., VDDQ = Max., CL = 0pF VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF VDDQ = 1.8V, FREFERENCE CLOCK = 250MHz, CL = 15pF VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF VDDQ = 1.8V, FREFERENCE CLOCK = 250MHz, CL = 15pF Typ. 20 0.1 10 20 20 25 20 40 Max 30 0.3 20 30 30 40 40 80 Unit mA mA A/MHz A/MHz mA mA
NOTES: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. The termination resistors are excluded from these measurements. 3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL
Symbol VDIF VX VTHI tR, tF Parameter Input Signal Swing(1) Differential Input Signal Crossing Point Input Signal Edge Rate
(4) (2)
Value 1 900 Crossing Point 1
Units V mV V V/ns
Input Timing Measurement Reference Level(3)
NOTES: 1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions. 2. A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR LVEPECL(1)
Symbol Parameter Input Characteristics IIH Input HIGH Current(6) IIL Input LOW Current(6) VIK Clamp Diode Voltage VIN DC Input Voltage VCM DC Common Mode Input Voltage(3,5) VREF Single-Ended Reference Voltage(4,5) VIH DC Input HIGH VIL DC Input LOW Test Conditions VDD = 2.6V VI = VDDQ/GND VDD = 2.6V VI = GND/VDDQ VDD = 2.4V, IIN = -18mA Min. -- -- -- - 0.3 915 -- 1275 555 Typ.(2) -- -- - 0.7 -- 1082 1082 -- -- Max 5 5 - 1.2 3.6 1248 -- 1620 875 Unit A V V mV mV mV mV
NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. Typical values are at VDD = 2.5V, +25C ambient. 3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 4. For single-ended operation while in differential mode, A/VREF is tied to the DC voltage VREF. 5. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 6. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
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IDT5T905 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVEPECL
Symbol VDIF VX VTHI tR, tF Parameter Input Signal Swing(1) Differential Input Signal Crossing Point Input Signal Edge Rate
(4) (2)
Value 732 1082 Crossing Point 1
Units mV mV V V/ns
Input Timing Measurement Reference Level(3)
NOTES: 1. The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions. 2. A 1082mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR 2.5V LVTTL(1)
Symbol Parameter Input Characteristics IIH Input HIGH Current(10) IIL Input LOW Current(10) VIK Clamp Diode Voltage VIN DC Input Voltage Single-Ended Inputs(2) VIH DC Input HIGH VIL DC Input LOW Differential Inputs VDIF DC Differential Voltage(3,9) VCM DC Common Mode Input Voltage(4,9) VIH DC Input HIGH(5,6,9) VIL DC Input LOW(5,7,9) VREF Single-Ended Reference Voltage(5,9) Output Characteristics VOH Output HIGH Voltage VOL Output LOW Voltage Test Conditions VDD = 2.6V VI = VDDQ/GND VDD = 2.6V VI = GND/VDDQ VDD = 2.4V, IIN = -18mA Min. -- -- -- - 0.3 1.7 -- 0.2 1150 VREF + 100 -- -- IOH = -12mA IOH = -100A IOL = 12mA IOL = 100A VDDQ - 0.4 VDDQ - 0.1 -- -- Typ.(8) -- -- - 0.7 Max 5 5 - 1.2 +3.6 -- 0.7 -- 1350 -- VREF - 100 -- -- -- 0.4 0.1 Unit A V V V V V mV mV mV mV V V V V
1250
1250
NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. For 2.5V LVTTL single-ended operation, the RxS pin is tied HIGH and A/VREF is tied to GND. 3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 5. For single-ended operation, in differential mode, A/VREF is tied to the DC voltage VREF. 6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 7. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 8. Typical values are at VDD = 2.5V, VDDQ = VDD, +25C ambient. 9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 10. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
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IDT5T905 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS FOR 2.5V LVTTL OUTPUTS(1)
Symbol IDDQ IDDQQ IDDD IDDDQ ITOT ITOTQ Parameter Quiescent VDD Power Supply Current Quiescent VDDQ Power Supply Current Dynamic VDD Power Supply Current per Output Dynamic VDDQ Power Supply Current per Output Total Power VDD Supply Current Total Power VDDQ Supply Current Test Conditions(2) VDDQ = Max., Reference Clock = LOW(3) Outputs enabled, All outputs unloaded VDDQ = Max., Reference Clock = LOW(3) Outputs enabled, All outputs unloaded VDD = Max., VDDQ = Max., CL = 0pF VDD = Max., VDDQ = Max., CL = 0pF VDDQ = 2.5V, FREFERENCE CLOCK = 100MHz, CL = 15pF VDDQ = 2.5V, FREFERENCE CLOCK = 200MHz, CL = 15pF VDDQ = 2.5V, FREFERENCE CLOCK = 100MHz, CL = 15pF VDDQ = 2.5V, FREFERENCE CLOCK = 200MHz, CL = 15pF Typ. 20 0.1 15 30 20 30 30 70 Max 30 0.3 20 40 40 50 50 100 Unit mA mA A/MHz A/MHz mA mA
NOTES: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. The termination resistors are excluded from these measurements. 3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 2.5V LVTTL
Symbol VDIF VX VTHI tR, tF Parameter Input Signal Swing(1) Differential Input Signal Crossing Point Input Signal Edge Rate(4)
(2)
Value VDD VDD/2 Crossing Point 2.5
Units V V V V/ns
Input Timing Measurement Reference Level(3)
NOTES: 1. A nominal 2.5V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions. 2. A nominal 1.25V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 2.5V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 2.5V LVTTL
Symbol VIH VIL VTHI tR, tF Parameter Input HIGH Voltage Input LOW Voltage Input Timing Measurement Reference Level(1) Input Signal Edge Rate(2) Value VDD 0 VDD/2 2 Units V V V V/ns
NOTES: 1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment. 2. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.
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IDT5T905 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR 1.8V LVTTL(1)
Symbol Parameter Input Characteristics IIH Input HIGH Current(12) IIL Input LOW Current(12) VIK Clamp Diode Voltage DC Input Voltage VIN Single-Ended Inputs(2) VIH DC Input HIGH DC Input LOW VIL Differential Inputs VDIF DC Differential Voltage(3,9) VCM DC Common Mode Input Voltage(4,9) VIH DC Input HIGH(5,6,9) VIL DC Input LOW(5,7,9) Single-Ended Reference Voltage(5,9) VREF Output Characteristics VOH Output HIGH Voltage VOL Output LOW Voltage Test Conditions VDD = 2.6V VI = VDDQ/GND VDD = 2.6V VI = GND/VDDQ VDD = 2.4V, IIN = -18mA Min. -- -- -- - 0.3 1.073(10) -- 0.2 825 VREF + 100 -- -- IOH = -6mA IOH = -100A IOL = 6mA IOL = 100A VDDQ - 0.4 VDDQ - 0.1 -- -- Typ.(8) -- -- - 0.7 Max 5 5 - 1.2 VDDQ + 0.3 -- 0.683(11) -- 975 -- VREF - 100 -- -- -- 0.4 0.1 Unit A V V V V V mV mV mV mV V V V V
900
900
NOTES: 1. See RECOMMENDED OPERATING RANGE table. 2. For 1.8V LVTTL single-ended operation, the RxS pin is allowed to float or tied to VDD/2 and A/VREF is tied to GND. 3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching to a new state. 4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only. 5. For single-ended operation in differential mode, A/VREF is tied to the DC voltage VREF. The input is guaranteed to toggle within 200mV of VREF when VREF is constrained within +600mV and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the A input. To guarantee switching in voltage range specified in the JEDEC 1.8V LVTTL interface specification, VREF must be maintained at 900mV with appropriate tolerances. 6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode. 7. Voltage required to maintain a logic LOW, single-ended operation in differential mode. 8. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25C ambient. 9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. The correct input interface table should be referenced. 10. This value is the worst case minimum VIH over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIH = 0.65 * VDD where VDD is 1.8V 0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated worst case value ( VIH = 0.65 * [1.8 - 0.15V]) rather than reference against a nominal 1.8V supply. 11. This value is the worst case maximum VIL over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIL = 0.35 * VDD where VDD is 1.8V 0.15V. However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated worst case value ( VIH = 0.35 * [1.8 + 0.15V]) rather than reference against a nominal 1.8V supply. 12. For differential mode (RxS = LOW), A and A/VREF must be at the opposite rail.
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IDT5T905 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS FOR 1.8V LVTTL OUTPUTS(1)
Symbol IDDQ IDDQQ IDDD IDDDQ ITOT ITOTQ Parameter Quiescent VDD Power Supply Current Quiescent VDDQ Power Supply Current Dynamic VDD Power Supply Current per Output Dynamic VDDQ Power Supply Current per Output Total Power VDD Supply Current Total Power VDDQ Supply Current Test Conditions(2) VDDQ = Max., Reference Clock = LOW(3) Outputs enabled, All outputs unloaded VDDQ = Max., Reference Clock = LOW(3) Outputs enabled, All outputs unloaded VDD = Max., VDDQ = Max., CL = 0pF VDD = Max., VDDQ = Max., CL = 0pF VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF VDDQ = 1.8V, FREFERENCE CLOCK = 200MHz, CL = 15pF VDDQ = 1.8V, FREFERENCE CLOCK = 100MHz, CL = 15pF VDDQ = 1.8V, FREFERENCE CLOCK = 200MHz, CL = 15pF Typ. 20 0.1 20 20 20 30 20 45 Max 30 0.3 30 30 30 40 40 80 Unit mA mA A/MHz A/MHz mA mA
NOTES: 1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations. 2. The termination resistors are excluded from these measurements. 3. If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 1.8V LVTTL
Symbol VDIF VX VTHI tR, tF Parameter Input Signal Swing(1) Differential Input Signal Crossing Point Input Signal Edge Rate
(4) (2)
Value VDDI VDDI/2 Crossing Point 1.8
Units V mV V V/ns
Input Timing Measurement Reference Level(3)
NOTES: 1. VDDI is the nominal 1.8V supply (1.8V 0.15V) of the part or source driving the input. A nominal 1.8V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VDIF (AC) specification under actual use conditions. 2. A nominal 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. Compliant devices must meet the VX specification under actual use conditions. 3. In all cases, input waveform timing is marked at the differential cross-point of the input signals. 4. The input signal edge rate of 1.8V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 1.8V LVTTL
Symbol VIH VIL VTHI tR, tF Parameter Input HIGH Voltage(1) Input LOW Voltage Input Timing Measurement Reference Level(2) Input Signal Edge Rate(3) Value VDDI 0 VDDI/2 2 Units V V mV V/ns
NOTES: 1. VDDI is the nominal 1.8V supply (1.8V 0.15V) of the part or source driving the input. 2. A nominal 900mV timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment. 3. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.
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IDT5T905 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE(6)
Symbol Parameter Skew Parameters Same Device Output Pin-to-Pin Skew(1) tSK(O) tSK(P)(2) dT(4) tSK(PP) Pulse Skew(3) Duty Cycle Part-to-Part Skew(5) Min. Single-Ended and Differential Modes Single-Ended in Differential Mode (DSE) Single-Ended and Differential Modes Single-Ended in Differential Mode (DSE) Single-Ended and Differential Modes Single-Ended in Differential Mode (DSE) Propagation Delay tPLH tPHL tR tF fO Output Rise Time (20% to 80%) Output Fall Time (20% to 80%) Frequency Range (HSTL/eHSTL outputs) 2.5V / 1.8V LVTTL Outputs HSTL / eHSTL Outputs 2.5V / 1.8V LVTTL Outputs HSTL / eHSTL Outputs Frequency Range (2.5V/1.8V LVTTL outputs) Output Gate Enable/Disable Delay tPGE tPGD Output Gate Enable to Qn Output Gate Enable to Qn Driven to GL Designated Level 350 350 350 350 -- -- -- -- -- -- -- -- -- -- -- -- 1050 1350 1050 1350 250 200 3.5 3 ns ns ps MHz ps Propagation Delay A to Qn -- -- 2.5 ns -- -- -- -- 40 -- -- Typ. -- 25 -- 300 -- -- 300 Max 25 -- 300 -- 60 300 -- Unit ps ps % ps
NOTES: 1. Skew measured between all outputs under identical input and output interfaces, transitions, and load conditions on any one device. 2. For only 1.8V/2.5V LVTTL and eHSTL outputs. 3. Skew measured is difference between propagation times tPLH and tPHL of any output under identical input and output interfaces, transitions, and load conditions on any one device. 4. For only HSTL outputs. 5. Skew measured is the magnitude of the difference in propagation times between any outputs of two devices, given identical transitions and load conditions at identical VDD/VDDQ levels and temperature. 6. Guaranteed by design.
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IDT5T905 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
AC DIFFERENTIAL INPUT SPECIFICATIONS(1)
Parameter Reference Clock Pulse Width HIGH or LOW (HSTL/eHSTL outputs)(2) Reference Clock Pulse Width HIGH or LOW (2.5V / 1.8V LVTTL outputs)(2) HSTL/eHSTL/1.8V LVTTL/2.5V LVTTL VDIF VIH VIL LVEPECL VDIF VIH VIL AC Differential Voltage(3) AC Input HIGH
(4,5)
Symbol tW
Min. 1.73 2.17 400 Vx + 200 -- 400 1275 --
Typ. -- -- -- -- -- -- -- --
Max -- -- -- -- Vx - 200 -- -- 875
Unit ns
mV mV mV mV mV mV
AC Input LOW(4,6) AC Differential Voltage(3) AC Input HIGH(4) AC Input LOW
(4)
NOTES: 1. For differential input mode, RxS is tied to GND. 2. Both differential input signals should not be driven to the same level simultaneously. The input will not change state until the inputs have crossed and the voltage range defined by VDIF has been met or exceeded. 3. Differential mode only. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. The AC differential voltage must be achieved to guarantee switching to a new state. 4. For single-ended operation, A/VREF is tied to DC voltage (VREF). Refer to each input interface's DC specification for the correct VREF range. 5. Voltage required to switch to a logic HIGH, single-ended operation only. 6. Voltage required to switch to a logic LOW, single-ended operation only.
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IDT5T905 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
AC TIMING WAVEFORMS
1/fo
tW A
tW
VIH VTHI VIL VIH VTHI VIL
A
tPLH Qn tSK(O) Qm
tPHL VOH VTHO VOL tSK(O) VOH VTHO VOL
Propagation and Skew Waveforms
NOTES: 1. tPHL and tPLH signals are measured from the input passing through VTHI or input pair crossing to Qn passing through VTHO. 2. Pulse Skew is calculated using the following expression: tSK(P) = | tPHL - tPLH | where tPHL and tPLH are measured on the controlled edges of any one output from rising and falling edges of a single pulse. Please note that the tPHL and tPLH shown are not valid measurements for this calculation because they are not taken from the same pulse.
A
VIH VTHI VIL VIH VTHI VIL VIH VTHI VIL tPLH VIH VTHI VIL tPGD tPGE VOH VTHO VOL
A
GL
G
Qn
Gate Disable/Enable Showing Runt Pulse Generation
NOTE: As shown, it is possible to generate runt pulses on gate disable and enable of the outputs. It is the user's responsibility to time their Gx signals to avoid this problem.
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IDT5T905 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
TEST CIRCUITS AND CONDITIONS
VDDI
R1 VIN 3 inch, ~50 Transmission Line VDD R2 VDDI A VDDQ
Pulse Generator
VIN 3 inch, ~50 Transmission Line
D.U.T.
R1 A
R2
Test Circuit for Differential Input(1)
DIFFERENTIAL INPUT TEST CONDITIONS
Symbol R1 R2 VDDI VDD = 2.5V 0.1V 100 100 VCM*2 HSTL: Crossing of A and A eHSTL: Crossing of A and A VTHI LVEPECL: Crossing of A and A 1.8V LVTTL: VDDI/2 2.5V LVTTL: VDD/2
NOTE: 1. This input configuration is used for all input interfaces. For single-ended testing, the VIN input is tied to GND. For testing single-ended in differential input mode, the VIN is left floating.
Unit V
V
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IDT5T905 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
VDD
VDDQ
VDDQ
R1
D.U.T.
Qn
CL
R2
Test Circuit for SDR Outputs
SDR OUTPUT TEST CONDITIONS
Symbol CL R1 R2 VTHO VDD = 2.5V 0.1V VDDQ = Interface Specified 15 100 100 VDDQ / 2 pF V Unit
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IDT5T905 2.5V SINGLE DATA RATE 1:5 CLOCK BUFFER TERABUFFER
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX X XXXXX Device Type Package Package
I PG
-40C to +85C (Industrial) Thin Shrink Small Outline Package
5T905
2.5V Single Data Rate 1:5 Clock Buffer TerabufferTM
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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